1. Field of Invention
The present invention relates to image scaling. More particularly, the present invention relates to method and apparatus for image scaling with a specified intermediate clock.
2. Description of Related Art
FIG. 1 shows a conventional image scaler whereby a source image with a 720×240 resolution is scaled to an output image with a 640×480 resolution. The source image is input into the image scaler using an input clock signal with a frequency of 13.5 MHz (Stage I), and the vertical resolution is initially scaled up from 240 lines to 480 lines while the horizontal resolution thereof remains unchanged. An intermediate image having a resolution 720×480 is thus generated and transferred to the next stage using an intermediate clock signal with a frequency of 27 MHz (Stage II). Then, the horizontal resolution of the intermediate image is scaled down from 720 pixels to 640 pixels while the vertical resolution thereof remains unchanged, and therefore the output image is output using an output clock signal with a frequency of 25.2 MHz (Stage III).
Therefore, three clock domains are involved in the scaling of the source image, which necessitates two PLLs (phase-locked loops). Moreover, a line buffer and pixel buffer are required respectively for vertical and horizontal scaling.
Alternatively, the source image may be scaled in another manner which necessitates only one PLL. The frequency of the intermediate clock signal used to generate and transfer the intermediate image may be the same as that of the input or output clock signal so that only the PLL for generation of the output clock signal must be included in the image scaler. However, this will adversely enlarge the size of the horizontal pixel buffer.